CPE 626 Advanced VLSI Design, Fall 2004
=======================================

HOMEWORK #2

Issued: 9/29/2004
Dues: 10/13/2004


This homework offers hands-on-experience in Xilinx System Generator.
Read Getting Started Tutorial with System Generator
at the following address: http://www.ece.uah.edu/~milenka/cpe626-04F/secure/sysgen/

Assignment:

Use System Generator under Simulink environment
running under MATLAB to design a 12x8 MAC (Multiply-Accumulator).

Directions:

- Multiplier input data widths of 12 bits and 8 bits are signed data.
- Multiplier output width of 20 bits.
- Accumulator output width of 24 bits.
- Accumulator has a reset input.
- Use a ramp function for both of the MAC inputs and 
  a step function for the reset signal.
- Set device to Virtex-II (2v1000 –4 fg456).
- 

Deliverables: 
0) Up to 2 pages of description of your work
1) Design and Simulation using Xilinx Blockset in Simulink
2) Results of simulation (functional and post-place & route) in Xilinx ISE
3) Synthesis report
4) Power report
5) Floorplan report